Senior FPGA Verification Engineer

Anduril IndustriesBoulder, Colorado, United States

seniorFull-timePosted 16 Oct 2026

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Skills in this posting

python
c++
linux
computer vision
git
testing

About the role

<div class="content-intro">Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.</div><h3>ABOUT THE TEAM&nbsp;&nbsp;</h3>

The Anduril Imaging team develops&nbsp;state-of-the-art&nbsp;imaging systems across both hardware and software, deployed to tackle the most significant security challenges of America and its allies.&nbsp;&nbsp;The team is heavily involved in&nbsp;utilizing&nbsp;computer vision, perception, electro-optical, infrared, and sensor data to give our war fighters and allies an advantage.&nbsp;&nbsp;&nbsp;&nbsp;

<h3>ABOUT THE JOB&nbsp;&nbsp;</h3>

The Imaging team is seeking a Senior FPGA Verification Engineer to help design a new product lines. In this role, you will work closely with an interdisciplinary technical team to define, complete the design and analysis, build prototypes leading to ground and flight testing, and mature the prototypes into products. &nbsp;

<ul>

<li>Verification environment architecture and design using&nbsp;tools like&nbsp;SystemVerilog&nbsp;or&nbsp;OVM/UVM&nbsp;</li>

<li>Creation of written test plan, testcases, code coverage tracking, and functional coverage tracking&nbsp;</li>

<li>Testbench development for the verification of RTL blocks using VHDL or&nbsp;SystemVerilog&nbsp;</li>

<li>Recommend new tools and practices for continuous improvement in the group's ASIC / FPGA verification flow&nbsp;</li>

<li>Contribute to engineering estimates for new program pursuits.&nbsp;</li>

<li>Provide technical leadership for project verification teams by breaking down work, planning activities, and reporting status&nbsp;</li>

</ul>

<h4>REQUIRED QUALIFICATIONS&nbsp;&nbsp;</h4>

<ul>

<li>A&nbsp;Bachelor's in Electrical Engineering, Computer Engineering, or a related technical field is typically&nbsp;required.&nbsp;&nbsp;</li>

<li>8+ years of experience developing HDL firmware for FPGA devices&nbsp;&nbsp;&nbsp;</li>

<li>Demonstrated experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.&nbsp;</li>

<li>experience developing and simulating RTL designs using VHDL and/or Verilog in a professional FPGA or ASIC development environment.&nbsp;</li>

<li>Proven ability to design, implement, and execute verification testbenches for RTL blocks using VHDL and/or&nbsp;SystemVerilog.&nbsp;</li>

<li>experience applying chip-level verification methodologies, including constrained-random testing, functional coverage analysis, and assertion-based verification (SystemVerilog)&nbsp;</li>

<li>Experience using revision control systems such as Git or Subversion to manage source code, collaborate across engineering teams, and&nbsp;maintain&nbsp;configuration integrity.&nbsp;</li>

<li>Eligible to obtain and&nbsp;maintain&nbsp;an active U.S. Secret security clearance&nbsp;&nbsp;</li>

</ul>

<h4>PREFERRED QUALIFICATIONS&nbsp;&nbsp;&nbsp;</h4>

<ul>

<li>Experience with ASIC/FPGA lab validation and debug using standard lab equipment, along with familiarity with DFT, manufacturability, and production test concepts.&nbsp;</li>

<li>Proficiency&nbsp;with Unix/Linux environments,&nbsp;scripting&nbsp;or software development (C, C++, Python, Perl, or shell), and industry-standard ASIC/FPGA simulation and synthesis tools such as&nbsp;QuestaSim,&nbsp;Synplify, Quartus, or&nbsp;Vivado.&nbsp;</li>

</ul><div class="content-pay-transparency"><div class="pay-input"><div class="title">US Salary Range</div><div class="pay-range">$165,000&mdash;$218,000 USD</div></div></div><div class="content-conclusion">The salary range for

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