Principal ASIC Synthesis and Timing Engineer

<div class="content-intro"><p data-renderer-start-pos="41">K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by over $1 billion in total funding from leading investors including Altimeter Capital, ICONIQ, Kleiner Perkins, Lightspeed Venture Partners, Redpoint Ventures, and T. Rowe Price — and with over $1 billion in signed contracts across commercial and US government customers, we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space.</p>

<p data-renderer-start-pos="570">The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits.</p>

<p data-renderer-start-pos="994">With multiple launches in 2027 and plans to scale to 100 satellites a year, we're Building Bigger — helping develop the solar system and build toward a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a high-growth Series D-funded company, we'd love for you to apply.</p></div><p><strong><span data-contrast="auto">The Role</span></strong><span data-ccp-props="{}"> </span></p>

<p><span data-contrast="auto">We are looking for a Principal ASIC Synthesis and Timing Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the constraints development and validation—from RTL handoff to synthesis —and collaborate closely with architecture, RTL design, DFT, and physical design team. This role also involves managing external physical design partners, driving convergence of schedule and ensuring first-pass silicon success in advanced FinFET technologies. You’ll be a key contributor in achieving timing closure, optimizing PPA, and supporting design integration with external partners. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most powerful, rapidly designed and rapidly manufactured satellites ever deployed in space. In your first 6 months, you will develop and implement new SoC sub-systems for satellite communications and beyond. In your first two years, you will have contributed to developing cutting-edge SoCs that will fly in space.</span><span data-ccp-props="{"335551550":6,"335551620":6}"> </span></p>

<p><strong><span data-contrast="auto">Responsibilities</span></strong><span data-ccp-props="{"335551550":6,"335551620":6}"> </span></p>

<ul>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span data-contrast="auto">Own the complete RTL-to-Synthesis flow: Do synthesis at block and top level, Work with physical design team to integrate the floorplanning information for physical synthesis. </span></li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area (PPA).</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Drive timing closure across multiple voltage and process corners, including sign-off with foundry-qualified tools.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Own Lint, CDC and UPF checks and drive collaboration to close out issues. </li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Develop an end to end formal verification methodology without any gap to deliver on full confidence functionality between the RTL and the  post layout netlist.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Manage and technically guide external physical design partners and service vendors, ensuring alignment on milestones, deliverables, and quality standards.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Support chip bring-up and debug through close collaboration with post-silicon and test teams.</li>

<li data-leveltext="" data-font="Symbol" data-listid="12" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1">Support your product through production and spaceflight. <span data-ccp-props="{}"> </span></li>

</ul>

<p><strong><span data-contrast="auto">Qualifications</span></strong><span data-ccp-props="{}"> </span></p>

<ul>

<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226":"Symbol","469769242":[8226],"469777803":"left","469777804":"","469777815":"hybridMultilevel"}" data-aria-posinset="1" data-aria-level="1"><span class="NormalTextRun SCXW207735684 BCX0">B</span><span class="NormalTextRun SCXW207735684 BCX0">.S. or M.S.</span><span class="NormalTextRun SCXW207735684 BCX0"> in Electrical Engineering, Computer Engineering, or related field</span></li>

<li data-leveltext="" data-font="Symbol" data-listid="13" data-list-defn-props="{"335552541":1,"335559685":720,"335559991":360,"469769226"