Senior Electrical Engineer, FPGA Development

True AnomalyLong Beach, CA

seniorPosted 23 Sept 2026

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Skills in this posting

python
c++

About the role

<div class="content-intro">Space is a warfighting domain. True Anomaly seeks those with the talent and ambition to build the technology that secures it.

OUR MISSION

True Anomaly delivers decisive capabilities for space superiority. We build autonomous spacecraft, advanced payloads, mission software, and space-based interceptors — enabling the U.S. and its Allies to secure the space environment and counter threats from the ultimate high ground.

OUR VALUES

<ul>

<li class="ms-outlook-mobile-reference-message">Be the offset.&nbsp;We create asymmetric advantages with creativity and ingenuity.</li>

<li class="ms-outlook-mobile-reference-message">What would it take?&nbsp;We challenge assumptions to deliver ambitious results.</li>

<li class="ms-outlook-mobile-reference-message">It’s the people.&nbsp;Our team is our competitive advantage and we are better together.</li>

</ul></div>YOUR MISSION

True Anomaly is&nbsp;seeking&nbsp;a talented and experienced Senior FPGA Developer to lead the architecture, implementation, and verification of complex FPGA-based systems for our spacecraft. In this role, you will own your technical domain end-to-end — from requirements capture and architecture definition through simulation, integration, and on-orbit support — while managing ambiguity and driving cross-team delivery with minimal oversight. You will define FPGA-to-CPU/SoC interface architectures, lead verification planning across full digital subsystems, and bring a system-aware perspective that balances performance, cost, and risk across disciplines. As a senior contributor, you will mentor peers, raise the technical bar across the team, and introduce&nbsp;new approaches&nbsp;to complex problems. You will collaborate closely with avionics, embedded software, and test teams to build high-reliability, radiation-tolerant firmware solutions that are fielded on real spacecraft.&nbsp;

RESPONSIBILITIES

<ul>

<li>Lead the architecture and implementation of complex FPGA systems with multiple clock domains, high-speed interfaces, and stringent reliability requirements&nbsp;</li>

<li>Own end-to-end FPGA development: requirements capture, functional block definition, HDL coding, simulation, synthesis, timing closure, and hardware integration&nbsp;</li>

<li>Lead multi-board digital backplane and payload data bus design, driving compliance, margin validation, and derating analysis&nbsp;</li>

<li>Define and manage verification and validation plans for full digital subsystems, integrating FPGA verification activities with system-level test&nbsp;</li>

<li>Define FPGA-to-CPU/SoC interface architectures and collaborate with embedded software teams on protocol design and integration&nbsp;</li>

<li>Develop and integrate COTS and custom IP cores into complete, production-ready solutions&nbsp;</li>

<li>Implement radiation mitigation strategies including TMR, ECC, and scrubbing for space applications&nbsp;</li>

<li>Lead cross-team delivery of FPGA development milestones, managing dependencies and setting clear checkpoints&nbsp;</li>

<li>Mentor peers and junior engineers, elevating design&nbsp;quality&nbsp;and development practices across the team&nbsp;</li>

<li>Develop and&nbsp;maintain&nbsp;design documentation, ICDs, verification plans, and test reports&nbsp;</li>

<li>Participate in all aspects of the product development lifecycle, from concept through production, integration, and launch&nbsp;</li>

</ul>

QUALIFICATIONS

<ul>

<li>Bachelor's degree in Electrical Engineering, Computer Engineering, or related field&nbsp;</li>

<li>5+ years of professional experience in FPGA design and development&nbsp;</li>

<li>Deep&nbsp;expertise&nbsp;in VHDL and/or Verilog and FPGA synthesis flows&nbsp;</li>

<li>Experience with Microsemi/Microchip, Xilinx/AMD, or Intel/Altera FPGA families and associated toolsets&nbsp;</li>

<li>Experience with simulation and verification tools such as&nbsp;ModelSim,&nbsp;QuestaSim, or similar&nbsp;</li>

<li>Experience designing and implementing high-speed Ethernet interfaces in FPGA fabric, including MAC/PHY integration, UDP/TCP offload, and high-throughput data path design&nbsp;</li>

<li>Experience with Layer 2 Ethernet switch development, including frame&nbsp;forwarding, VLAN handling, and port arbitration&nbsp;</li>

<li>Experience with other high-speed serial interfaces (PCIe) and common bus protocols (SPI, I2C, UART)&nbsp;</li>

<li>Experience with radiation mitigation techniques for space-grade digital logic&nbsp;</li>

<li>Experience reading and interpreting electrical schematics and collaborating with hardware design teams&nbsp;</li>

<li>Excellent written and verbal communication skills&nbsp;</li>

</ul>

PREFERRED SKILLS AND EXPERIENCE

<ul>

<li>Experience with spacecraft FPGA development and space-qualified or radiation-hardened device families (PolarFire, ProASIC3, SmartFusion2, etc.)&nbsp;</li>

<li>Experience defining and executing FPGA-to-CPU/SoC interface architectures in collaboration with embedded software teams&nbsp;</li>

<li>Familiarity with SpaceWire and other spacecraft-specific data bus standards&nbsp;</li>

<li>Familiarity with signal integrity analysis and high-speed digital design practices&nbsp;</li>

<li>Exposure to software development in C, C++, or Python for firmware integration and test scripting&nbsp;</li>

<li>Knowledge of schematic capture tools (Altium Designer preferred)&nbsp;</li>

<li>Experience working in a fast-paced, startup environment or a similarly dynamic setting&nbsp;</li>

</ul>

COMPENSATION

<ul>

<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Base Salary: $150,000-$220,000</li>

<li data-leveltext="" data-font="Symbol" data-listid="2" data-list-defn-props="{&quot;335552541&quot;:1,&quot;335559685&quot;:720,&quot;335559991&quot;:360,&quot;469769226&quot;:&quot;Symbol&quot;,&quot;469769242&quot;:[8226],&quot;469777803&quot;:&quot;left&quot;,&quot;469777804&quot;:&quot;&quot;,&quot;469777815&quot;:&quot;hybridMultilevel&quot;}" data-aria-posinset="1" data-aria-level="1">Equity + Benefits including Health, Dental, Vision, HRA/HSA options, PTO and paid holidays, 401K, Parental Leave&nbsp;</li>

</ul>

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